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99 lines
3.6 KiB
99 lines
3.6 KiB
/* SharpLr35902.Macros.h |
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* |
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* Macros to assist with Sharp LR35902 emulation. |
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*/ |
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#pragma once |
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#include "../../PlipSupport.h" |
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#define IDX_B 0b000 |
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#define IDX_C 0b001 |
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#define IDX_D 0b010 |
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#define IDX_E 0b011 |
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#define IDX_H 0b100 |
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#define IDX_L 0b101 |
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#define IDX_HL 0b110 |
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#define IDX_A 0b111 |
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#define ADDR_BC 0b00 |
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#define ADDR_DE 0b01 |
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#define ADDR_HLP 0b10 // HL+ |
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#define ADDR_HLM 0b11 // HL- |
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#define IDX_16_BC 0b00 |
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#define IDX_16_DE 0b01 |
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#define IDX_16_HL 0b10 |
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#define IDX_16_SP 0b11 |
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#define COND_NZ 0b00 |
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#define COND_Z 0b01 |
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#define COND_NC 0b10 |
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#define COND_C 0b11 |
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#define ZERO 7 |
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#define SUBTRACT 6 |
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#define HALFCARRY 5 |
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#define CARRY 4 |
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#define MEM_READ(addr) m_memory->GetByte(addr) |
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#define MEM_WRITE(addr, val) m_memory->SetByte(addr, val) |
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#define FETCH m_instr.push_back(MEM_READ(m_reg.pc++)) |
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#define FETCH_CYCLE(cycle) do { if(m_mcycle == (cycle)) { FETCH; } } while(0) |
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#define FETCH_ADDR(addr) m_instr.push_back(MEM_READ(addr)) |
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#define FETCH_ADDR_CYCLE(cycle, addr) do { if(m_mcycle == (cycle)) { FETCH_ADDR(addr); } } while(0) |
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#define FETCH_IMM_CYCLE(cycle) do { if(m_mcycle == (cycle)) { FETCH; } } while(0) |
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#define CYCLE(cycle) if(m_mcycle == (cycle)) |
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#define BEGIN_EXECUTE m_allowFetch = false |
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#define END_EXECUTE m_instr.clear(); m_mcycle = 2; m_allowFetch = true |
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#define NUM_MCYCLES(val) do { if(++m_mcycle > (val)) { END_EXECUTE; } } while(0) |
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#define OP_COND ((m_instr[0] >> 3) & 0b00000011) |
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#define OP_REG16(idx) ((m_instr[(idx)] >> 4) & 0b00000011) |
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#define OP_IDX(idx) ((m_instr[(idx)] >> 3) & 0b00000111) |
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#define OP_REG_X(idx) OP_IDX(idx) |
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#define OP_REG_Y(idx) (m_instr[(idx)] & 0b00000111) |
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#define REG_BC COMBINE16LE(m_reg.b, m_reg.c) |
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#define REG_DE COMBINE16LE(m_reg.d, m_reg.e) |
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#define REG_HL COMBINE16LE(m_reg.h, m_reg.l) |
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#define SET_PC_IMM m_reg.pc = (m_instr[2] << 8 | m_instr[1]) |
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#define SET_PC_STACK(cycle) \ |
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do { \ |
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CYCLE(cycle) { m_reg.pc &= 0xFF00; m_reg.pc |= STACK_POP; } \ |
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CYCLE((cycle) + 1) { m_reg.pc &= 0x00FF; m_reg.pc |= STACK_POP << 8; } \ |
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} while(0) |
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#define STACK_PUSH(val) m_memory->SetByte(--m_reg.sp, (val)) |
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#define STACK_PUSH_PC(cycle) \ |
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do { \ |
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CYCLE(cycle) { STACK_PUSH(m_reg.pc >> 8); } \ |
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CYCLE((cycle) + 1) { STACK_PUSH(m_reg.pc & 0xFF); } \ |
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} while(0) |
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#define STACK_POP m_memory->GetByte(m_reg.sp++) |
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#define FLAG_CLEAR(bit) BIT_CLEAR(m_reg.f, (bit)) |
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#define FLAG_FLIP(bit) BIT_FLIP(m_reg.f, (bit)) |
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#define FLAG_SET(bit) BIT_SET(m_reg.f, (bit)) |
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#define FLAG_TEST(bit) BIT_TEST(m_reg.f, (bit)) |
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#define CHECK_BIT_CARRY(val) do { if(val) FLAG_SET(CARRY); else FLAG_CLEAR(CARRY); } while(0) |
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#define CHECK_CARRY(val) do { if((val) & 0xFF00) FLAG_SET(CARRY); else FLAG_CLEAR(CARRY); } while(0) |
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#define CHECK_CARRY16(val) do { if((val) & 0xFFFF0000) FLAG_SET(CARRY); else FLAG_CLEAR(CARRY); } while(0) |
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#define CHECK_ADD_HALFCARRY(left, right) do { \ |
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if(((left) & 0x0F) + ((right) & 0x0F) > 0x0F) FLAG_SET(HALFCARRY); \ |
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else FLAG_CLEAR(HALFCARRY); } while(0) |
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#define CHECK_SUB_HALFCARRY(left, right) do { \ |
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if(((left) & 0x0F) - ((right) & 0x0F) < 0x00) FLAG_SET(HALFCARRY); \ |
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else FLAG_CLEAR(HALFCARRY); } while(0) |
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#define CHECK_ADD_HALFCARRY16(left, right) do { \ |
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if(((left) & 0x0FFF) + ((right) & 0x0FFF) > 0x0FFF) FLAG_SET(HALFCARRY); \ |
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else FLAG_CLEAR(HALFCARRY); } while(0) |
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#define CHECK_SUB_HALFCARRY16(left, right) do { \ |
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if(((left) & 0x0FFF) - ((right) & 0x0FFF) < 0x0000) FLAG_SET(HALFCARRY); \ |
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else FLAG_CLEAR(HALFCARRY); } while(0) |
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#define CHECK_ZERO(val) do { if((val)) FLAG_CLEAR(ZERO); else FLAG_SET(ZERO); } while(0)
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